A certain number of digital systems include several processors in order to provide improved performance, especially in order to make up for the frequency limitations of a single processor, and in particular for systems on chip. Each processor of such a system can synchronize its operation with the others and can share data by means of read/write operations in memory locations shared by all of the processors. In order to furnish access to the data with shortened response times and a large bandwidth, each processor has a cache memory containing a local copy of data from a shared memory location. Since the various processors may contain duplicate copies for the same memory location in their cache memory, it is necessary to maintain coherency between these cache memories. This coherency can be provided through software or hardware. The hardware solution makes it possible to optimize the exchange of data while reducing the cost of synchronization. In this way, whenever data in a cache memory is modified by a processor, the other cache memories of the other processors are automatically updated to accurately reflect this change.
FIG. 1 shows a method for monitoring traffic (snooping method) along a global bus connecting the cache memories of the processors to a shared memory by means of a bridge. The digital system 1 of FIG. 1 has processors 2 and 3 equipped respectively with processing units 21 and 31 and cache memories 22 and 32. The system 1 also has a bus 4 designed to facilitate the operations for producing coherency between the cache memories 22 and 32. The bus 4 connects the processors 2 and 3 to the bridge 5, the bridge 5 itself being connected to a shared memory 6 and to an input/output channel 7. The interface of each processor with the bus has 120 bits, 64 bits being reserved for the data and 56 bits being reserved for an address and the operation code.
The bridge 5 includes a memory controller as well as a logic circuit in order to conduct the traffic-monitoring transactions along the bus 4. The processors 2 and 3 and their cache memories 22 and 32 manage the memory traffic-monitoring transactions along the bus 4. The processors 2 and 3 use traffic-monitoring data to keep the contents of their cache memory coherent with the cache memory of the other processors.
A system such as this has disadvantages. The updating of the cache memories of the processors requires that the shared memory be accessed numerous times. The processors' response time to an external request is thus increased, the traffic along the bus is heavy and the system's overall electrical consumption is high.